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june 2004 i ? 2004 actel corporation ex family fpgas leading edge performance ? 240 mhz system performance 350 mhz internal performance 3.9 ns clock-to-out (pad-to-pad) specifications 3,000 to 12,000 available system gates maximum 512 flip-flops (using cc macros) 0.22 m cmos process technology up to 132 user-programmable i/o pins features high-performance, low-power antifuse fpga lp/sleep mode for additional power savings advanced small- footprint packages hot-swap compliant i/os single-chip solution nonvolatile live on power-up no power-up/down sequence required for supply voltages configurable weak-resis tor pull-up or pull-down for tristated outputs during power-up individual output slew rate control 2.5v, 3.3v, and 5.0v mixed-voltage operation with 5.0v input toleranc e and 5.0v drive strength software design support with actel designer and libero? integrated design environment (ide) tools up to 100% resource utilization with 100% pin locking deterministic timing unique in-system diagnostic and verification capability with silicon explorer ii boundary scan testing in compliance with ieee standard 1149.1 (jtag) fuselock? secure programming technology prevents reverse engineering and design theft product profile fuselock device ex64 ex128 ex256 capacity system gates ty p i c a l g a t e s 3,000 2,000 6,000 4,000 12,000 8,000 register cells dedicated flip-flops maximum flip-flops 64 128 128 256 256 512 combinatorial cells 128 256 512 maximum user i/os 84 100 132 global clocks hardwired routed 1 2 1 2 1 2 speed grades ?f, std, ?p ?f, std, ?p ?f, std, ?p temperature grades* c, i, a c, i, a c, i, a package (by pin count) tqfp csp 64, 100 49, 128 64, 100 49, 128 100 128, 180 note: *refer to the ex automotive family fpgas datasheet for details on automotive temperature offerings. v4.2
ex family fpgas ii v4.2 ordering information plastic device resources temperature grade offerings speed grade and temperature grade matrix contact your local actel represen tative for device availability. ex128 tq part number package type tq = thin quad flat pack (1.4mm pitch) cs = chip-scale package (0.8mm pitch) 100 package lead count application (ambient temperature range) i = industrial (-40?c to 85?c) a = automotive (-40?c to 125?c) pp = pre-production blank = commercial (0?c to 70?c) speed grade 64 dedicated flip-flops (3,000 system gates) ex64 = ex128 128 dedicated flip-flops (6,000 system gates) = ex256 256 dedicated flip-flops (12,000 s y stem gates) = standard speed blank= p approximately 30% faster than standard = f approximately 40% slower than standard = p user i/os (including clock buffers) device tqfp 64-pin tqfp 100-pin csp 49-pin csp 128-pin csp 180-pin ex64 41 56 36 84 ? ex128 467036100? ex256 ? 81 ? 100 132 note: package definitions: tqfp = thin quad flat pa ck, csp = chip scale package device\package tqfp 64-pin tqfp 100-pin csp 49-pin csp 128-pin csp 180-pin ex64 c, i, a c, i, a c, i, a c, i, a c, i, a ex128 c, i, a c, i, a c, i, a c, i, a c, i, a ex256 c, i, a c, i, a c, i, a c, i, a c, i, a notes: c = commercial i = industrial a = automotive ?f std ?p c ??? i ?? a ? notes: p = approximately 30% faster than standard ?f = approximately 40% slower than standard refer to the ex automotive family fpgas datasheet for details on auto motive temperature offerings.
v4.1 iii table of contents ex family fpgas ex family fpgas general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 ex family architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 other architectural features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 2.5v/3.3v/5.0v operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 2.5v lvcmos2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 3.3v lvttl electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 5.0v ttl electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 ex timing model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 output buffer delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 ac test loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 9 input buffer delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 c-cell delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -20 cell timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 temperature and voltage derating fact ors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 ex family timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 6 package pin assignments 64-pin tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 100-pin tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -3 49-pin csp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 128-pin csp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 180-pin csp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -11 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

ex family fpgas v4.2 1-1 ex family fpgas general description the ex family of fpgas is a low-cost solution for low- power, high-performance designs. the inherent low power attributes of the antifuse technology, coupled with an additional low st atic power mode, make these devices ideal for power-sensit ive applications. fabricated with an advanced 0.22 m cmos antifuse technology, these devices achieve high performance with no power penalty . ex family architecture actel's ex family is implemen ted on a high-voltage twin- well cmos process using 0.22m design rules. the ex family architecture uses a ?sea-of-modules? structure where the entire floor of th e device is covered with a grid of logic modules with vi rtually no chip area lost to interconnect elements or routing. interconnection among these logic modules is achieved using actel?s patented metal-to-metal programmable antifuse interconnect elements. the antifuse interconnect is made up of a combination of amorphous silicon and dielectric material with barrier metals and has an "on" state resistance of 25 ? with a capacitance of 1.0ff for low-signal impedance. the an tifuses are normally open circuit and, when programm ed, form a permanent low- impedance connection. actel?s ex family provides two types of logic modules, the register cell (r-cell) and the combinatorial cell (c-cell). the r-cell contains a flip-f lop featuring asynchronous clear, asynchronous preset, and clock enable (using the s0 and s1 lines) control signals ( figure 1-1 ). the r-cell registers feature programmable clock polarity selectable on a register-by-register basi s. this provides additional flexibility while allowing mapping of synthesized functions into the ex fpga. the clock source for the r- cell can be chosen from eith er the hard-wired clock or the routed clock. the c-cell implements a rang e of combinatorial functions up to five inputs ( figure 1-2 on page 1-2 ). inclusion of the db input and its associated inverter function enables the implementation of more than 4,000 combinatorial functions in the ex archit ecture in a single module. two c-cells can be combined together to create a flip- flop to imitate an r-cell via th e use of the cc macro. this is particularly useful wh en implementing non-timing- critical paths and when the design engineer is running out of r-cells. more information about the cc macro can be found in actel?s maximizing logic utilization in ex, sx and sx-a fpga devices using cc macros application note. figure 1-1 r-cell directconnect input clka, clkb, internal logic hclk cks ckp clr pset y dq routed data input s0 s1
ex family fpgas 1-2 v4.2 module organization c-cell and r-cell logic modules are arranged into horizontal banks called clusters, each of which contains two c-cells and one r-cell in a c-r-c configuration. clusters are further organized into modules called superclusters for improved design efficiency and device performance, as shown in figure 1-3 . each supercluster is a two-wide grouping of clusters. figure 1-2 c-cell figure 1-3 cluster organization d0 d1 d2 d3 db a0 b0 a1 b1 sa sb y supercluster cluster cluster r-cell c-cell d0 d1 d2 d3 db a0 b0 a1 b1 sa sb y directconnect input clka, clkb, internal logic hclk cks ckp clr pset y d q routed data input s0 s1
ex family fpgas v4.2 1-3 routing resources clusters and superclusters can be connected through the use of two innovative local routing resources called fastconnect and directconnect, which enable extremely fast and predictable interconnection of modules within clusters and superclusters ( figure 1-4 ). this routing architecture also dramatic ally reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance. directconnect is a horizontal routing resource that provides connections from a c-cell to its neighboring r- cell in a given supercluster. directconnect uses a hard- wired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns (?p speed grade). fastconnect enables horizontal routing between any two logic modules within a given supercluster and vertical routing with the supercluster immediately below it. only one programmab le connection is used in a fastconnect path, delivering maximum pin-to-pin propagation of 0.3 ns (?p speed grade). in addition to directconnect and fastconnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. actel?s segmented routing structure provides a variety of track lengths for extremely fast routing between superclusters. the exact combination of track lengths and antifuses within each path is chosen by the fully automatic place-and-route software to minimize signal propagation delays. figure 1-4 directconnect and fastconnect for superclusters superclusters directconnect no antifuses 0.1 ns routing delay fastconnect one antifuse 0.5 ns routing delay routing segments typically 2 antifuses max. 5 antifuses
ex family fpgas 1-4 v4.2 clock resources ex?s high-drive routing structure provides three clock networks. the first clock, called hclk, is hardwired from the hclk buffer to the clock select mux in each r-cell. hclk cannot be connected to combinational logic. this provides a fast propagation path for the clock signal, enabling the 3.9 ns cloc k-to-out (pad-to-pad) performance of the ex devices. the hard-wired clock is tuned to provide a clock skew of less than 0.1 ns worst case. if not used, the hclk pin must be tied low or high and must not be left floating. figure 1-5 describes the clock circuit used for the constant load hclk. hclk does not function until the fourth clock cycle each time the device is powered up to prevent false output levels due to any possible sl ow power-on-reset signal and fast start-up clock circuit. to activate hclk from the first cycle, the trst pin must be reserved in the design software and the pin must be tied to gnd on the board. (see the "trst, i/o boundary scan reset pin" on page 1- 26 ). the remaining two clocks (clka, clkb) are global routed clock networks that can be sourced from external pins or from internal logic signals (via the clkint routed clock buffer) within the ex device. clka and clkb may be connected to sequential cells or to combinational logic. if clka or clkb is sourced from internal logic signals, the external clock pin cannot be used for any other input and must be tied low or high and must not float. figure 1-6 describes the clka and clkb circuit used in ex devices. table 1-1 describes the possible connections of the routed clock networks, clka and clkb. unused clock pins must not be left floating and must be tied to high or low. figure 1-5 ex hclk clock pad constant load clock network hclkbuf figure 1-6 ex routed clock buffer clock network from internal logic clkbuf clkbufi clkint clkinti table 1-1 connections of routed clock networks, clka and clkb module pins c-cell a0, a1, b0 and b1 r-cell clka, clkb, s0, s1, pset, and clr i/o-cell en
ex family fpgas v4.2 1-5 other architectural features performance the combination of architec tural features described above enables ex devices to operate with internal clock frequencies exceeding 350 mhz for very fast execution of complex logic functions. th e ex family is an optimal platform upon which the functionality previously contained in cplds can be integrated. ex devices meet the performance goals of gate arrays, and at the same time, present significant improvements in cost and time to market. using timing-dri ven place-and-route tools, designers can achieve highly deterministic device performance. user security the actel fuselock advantag e ensures that unauthorized users will not be able to read back the contents of an actel antifuse fpga. in addition to the inherent strengths of the architecture, special security fuses that prevent internal probing and overwriting are hidden throughout the fabric of th e device. they are located such that they cannot be accessed or bypassed without destroying the rest of the device, making both invasive and more-subtle noninvasive attacks ineffective against actel antifuse fpgas. look for this symbol to ensure your valuable ip is secure. for more information, refer to actel's implementation of security in actel antifuse fpgas application note. i/o modules each i/o on an ex device can be configured as an input, an output, a tristate output, or a bidirectional pin. even without the inclusion of dedicated i/o registers, these i/ os, in combination with a rray registers, can achieve clock-to-out (pad-to-pad) timi ng as fast as 3.9 ns. i/o cells in ex devices do not contain embedded latches or flip- flops and can be inferred directly from hdl code. the device can easily interface with any other device in the system, which in turn enable s parallel design of system components and reduces overall design time. all unused i/os are configur ed as tristate outputs by actel's designer software, for maximum flexibility when designing new boards or migrating existing designs. each i/o module has an ava ilable pull-up or pull-down resistor of approximately 50k ? that can configure the i/o in a known state during power-up. just shortly before v cca reaches 2.5v, the resistor s are disabled and the i/os will be controlled by user logic. table 1-2 describes the i/o features of ex devices. for more information on i/os, refer to actel ex, sx-a, and rt54sx-s i/os application note. the ex family supports mi xed-voltage operation and is designed to tolerate 5. 0v inputs in each case. a detailed description of the i/o pins in ex devices can be found in "pin description" on page 1-26 . figure 1-7 fuselock fuselock table 1-2 i/o features function description input buffer threshold selection 5.0v ttl 3.3v lvttl 2.5v lvcmos2 nominal output drive 5.0v ttl/cmos 3.3v lvttl 2.5v lvcmos 2 output buffer ?hot-swap? capability i/o on an unpowered device does not sink current can be used for ?cold sparing? selectable on an individual i/o basis individually selectable low-slew option power-up individually selectable pull ups and pull downs during power-up (default is to power up in tristate) enables deterministic power-up of device v cca and v cci can be powered in any order
ex family fpgas 1-6 v4.2 hot swapping ex i/os are configured to be hot-swappable. during power-up/down (or partia l up/down), all i/os are tristated, provided v cca ramps up within a diode drop of v cci . v cca and v cci do not have to be stable during power-up/down, and they do not require a specific power-up or power-down sequence in order to avoid damage to the ex devices. in addition, all outputs can be programmed to have a w eak resistor pull-up or pull- down for output tristate at power-up. after the ex device is plugged into an el ectrically active system, the device will not degrade the reliability of or cause damage to the host system. the device's output pins are driven to a high impedance state until normal chip operating conditions are reached. please see the application note, actel sx-a and rt54sx-s devices in hot-swap and cold-sp aring applications , which also applies to the ex devices, for more information on hot swapping. power requirements power consumption is extrem ely low for the ex family due to the low capacitance of the antifuse interconnects. the antifuse architecture does not require active circuitry to hold a charge (as do sram or eprom), making it the lowest-power fpga archit ecture available today. low power mode the ex family has been designed with a low power mode. this feature, activate d with setting the special lp pin to high for a period longer than 800 ns, is particularly useful for batt ery-operated systems where battery life is a primary concer n. in this mode, the core of the device is turned off and the device consumes minimal power with low standby curr ent. in addition, all input buffers are turned off, and all outputs and bidirectional buffers are tristated when th e device enters this mode. since the core of the device is turned off, the states of the registers are lost. the device must be re-initialized when returning to normal operating mode. i/os can be driven during lp mode. for details, refer to the design for low power in actel antifuse fpgas application note under the section using the lp mode pin on ex devices. clock pins should be driven either high or low and should not float; otherwise, they will draw current and burn power. the device must be re-initialized when exiting lp mode. to exit the lp mode, the lp pin must be driven low for over 200s to allow for the charge pumps to power-up and device initialization can begin. table 1-3 illustrates the standby cu rrent of ex devices in lp mode. table 1-3 standby power of ex devices in lp mode typical conditions, v cca , v cci = 2.5v, t j = 25 c product low power standby current units ex64 100 a ex128 111 a ex256 134 a
ex family fpgas v4.2 1-7 figure 1-8 to figure 1-11 on page 1-8 show some sample power characteristics of ex devices. notes: 1. device filled with 16-bit counters. 2. v cca , v cci = 2.7v, device tested at room temperature. figure 1-8 ex dynamic power consumption ? high frequency notes: 1. device filled with 16-bit counters. 2. v cca , v cci = 2.7v, device tested at room temperature. figure 1-9 ex dynamic power consumption ? low frequency 0 50 100 150 200 250 300 50 100 150 200 frequency (mhz) power (mw) ex64 ex128 ex256 0 10 20 30 40 50 60 70 80 0 1020304050 frequency (mhz) power (mw) ex64 ex128 ex256
ex family fpgas 1-8 v4.2 figure 1-10 total dynamic power (mw) figure 1-11 system power at 5%, 10%, and 15% duty cycle 0 20 40 60 80 100 120 140 160 180 0 25 50 75 100 125 150 175 200 frequency (mhz) total dynamic power (mw) 32-bit decoder 8 x 8-bit counters sdram controller 0 2,000 4,000 6,000 8,000 10,000 12,000 0 102030405060 frequency (mhz) system power (uw) 5% dc 10% dc 15% dc
ex family fpgas v4.2 1-9 boundary scan testing (bst) all ex devices are ieee 1149.1 compliant. ex devices offer superior diagnostic and test ing capabilities by providing boundary scan testing (bst ) and probing capabilities. these functions ar e controlled through the special test pins (tms, tdi, tck, tdo and trst). the functionality of each pin is defined by two available modes: dedicated and flexible, and is described in table 1-4 . in the dedicated test mode, tck, tdi, and tdo are dedicated pins and cannot be used as regular i/os. in flexible mode (default mode), tms should be set high through a pull- up resistor of 10k ? . tms can be pulled low to initiate the test sequence. dedicated test mode in dedicated mode, all jtag pins are reserved for bst; designers cannot use them as regular i/os. an internal pull-up resistor is automatically enabled on both tms and tdi pins, and the tms pin will function as defined in the ieee 1149.1 (jtag) specification. to select dedicated mode, users need to reserve the jtag pins in actel's designer software by checking the "reserve jtag" box in "device selection wizard" ( figure 1-12 ). flexible mode in flexible mode, tdi, tck and tdo may be used as either user i/os or as jt ag input pins. the internal resistors on the tms and tdi pins are disabled in flexible jtag mode, and an external 10k ? pull-resistor to v cci is required on the tms pin. to select the flexible mode , users need to uncheck the "reserve jtag" box in "device selection wizard" in actel's designer software. the functionality of tdi, tck, and tdo pins is controlled by the bst tap controller. the tap controller receives two control inputs, tms and tck. upon power-up, the tap contro ller enters the test-logic- reset state. in this state, tdi, tck, and tdo function as user i/os. the tdi, tck, and tdo pins are transformed from user i/os into bst pins when the tms pin is low at the first rising edge of tck. the tdi, tck, and tdo pins return to user i/os when tm s is held high for at least five tck cycles. table 1-5 describes the different configuration requirements of bst pins and their functionality in different modes. trst pin the trst pin functions as a dedicated boundary-scan reset pin when the "reserve jtag test reset" option is selected as shown in figure 1-12 . an internal pull-up resistor is permanently enab led on the trst pin in this mode. it is recommended to connect this pin to gnd in normal operation to keep the jtag state controller in the test-logic-reset state. when jtag is being used, it can be left floating or be driven high. when the "reserve jtag test reset" option is not selected, this pin will functi on as a regular i/o. if unused as an i/o in the design, it will be configured as a tristated output. table 1-4 boundary scan pin functionality dedicated test mode flexible mode tck, tdi, tdo are dedicated bst pins tck, tdi, tdo are flexible and may be used as i/os no need for pull-up resistor for tms and tdi use a pull-up resistor of 10k ? on tms figure 1-12 device selection wizard table 1-5 boundary-scan pin configurations and functions mode designer "reserve jtag" selection tap controller state dedicated (jtag) checked any flexible (user i/o) un checked test-logic-reset flexible (jtag) unchecked any except test- logic-reset
ex family fpgas 1-10 v4.2 jtag instructions table 1-6 lists the supported instructions with the corresponding ir codes for ex devices. table 1-7 lists the codes returned after executing the idcode instruction for ex devices. note that bit 0 is always "1." bits 11-1 are always "02f", which is actel's manufacturer code. programming device programming is su pported through silicon sculptor series of progra mmers. in particular, silicon sculptor ii is a compact, robust, single-site and multi-site device programmer for the pc. with standalone software, silicon sculptor ii allows concurrent programming of multiple units from the same pc, ensuring the fastest programming times possible. each fuse is subseq uently verified by silicon sculptor ii to insure correct programming. in addition, integrity tests ensure that no extra fuses are programmed. silicon sculptor ii also provides extensive hardware self-testing capability. the procedure for programm ing an ex device using silicon sculptor ii is as follows: 1. load the .afm file 2. select the device to be programmed 3. begin programming when the design is ready to go to production, actel offers device volume-programming services either through distribution partners or via in-house programming from the factory. for more details on programming ex devices, please refer to the programming actel devices application note and the silicon sculptor ii user's guide . probing capabilities ex devices provide internal probing capability that is accessed with the jtag pins. the silicon explorer ii diagnostic hardware is used to control the tdi, tck, tms and tdo pins to select the desired nets for debugging. the user simply assigns the se lected internal nets in the silicon explorer ii software to the pra/prb output pins for observation. probing functionality is activated when the bst pins are in jtag mode and the trst pin is driven high or left floating. if the trst pin is held low, the tap controller will remain in the test-logic-reset state so no probing can be performe d. the silicon explorer ii automatically places the device into jtag mode, but the user must drive the trst pi n high or allow the internal pull-up resistor to pull trst high. when you select the "reserve probe pin" box as shown in figure 1-12 on page 1-9 , the layout tool reserves the pra and prb pins as dedicated outputs for probing. this "reserve" option is merely a guideline. if the layout tool requires that the pra and prb pins be user i/os to achieve successful layout, the tool will use these pins for user i/os. if you assign user i/os to the pra and prb pins and select the "reserve pr obe pin" option, designer layout will override the "res erve probe pin" option and place your user i/os on those pins. to allow for probing capabilities, the security fuse must not be programmed. programming the security fuse will disable the probe circuitry. table 1-8 on page 1-11 summarizes the possible device configurations for probing once the device leav es the "test-logic-reset" jtag state. silicon explorer ii probe silicon explorer ii is an integrated hardware and software solution that, in conjunction with actel?s designer software tools, a llow users to examine any of the internal nets of the device while it is operating in a prototype or a production system. the user can probe into an ex device via the pra and prb pins without changing the placement and routing of the design and without using any additional resources. silicon explorer table 1-6 jtag instruction code instructions (ir4: ir0) binary code extest 00000 sample / preload 00001 intest 00010 usercode 00011 idcode 00100 highz 01110 clamp 01111 diagnostic 10000 bypass 11111 reserved all others table 1-7 idcode for ex devices device revision bits 31-28 bits 27-12 ex64 0 8 40b2, 42b2 ex128 0 9 40b0, 42b0 ex256 0 9 40b5, 42b5 ex64 1 a 40b2, 42b2 ex128 1 b 40b0, 42b0 ex256 1 b 40b5, 42b5
ex family fpgas v4.2 1-11 ii's non-invasive method does not alter timing or loading effects, thus shortening the debug cycle. silicon explorer ii does not require re-layout or additional muxes to bring signals out to an external pin, which is necessary when using programmable logic devices from other suppliers. silicon explorer ii samples data at 100 mhz (asynchronous) or 66 mhz (syn chronous). silicon explorer ii attaches to a pc's standa rd com port, turning the pc into a fully functional 18-channel logic analyzer. silicon explorer ii allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds. the silicon explorer ii tool uses the bounda ry scan ports (tdi, tck, tms and tdo) to select the desired nets for verification. the selected intern al nets are assigned to the pra/prb pins for observation. figure 1-13 illustrates the interconnection between silicon explorer ii and the ex device to perform in-circuit verification. design considerations the tdi, tck, tdo, pra, and pr b pins should not be used as input or bidirectional port s. since these pins are active during probing, critical signals input through these pins are not available while probing. in addition, the security fuse should not be programmed because doing so disables the probe circuitry. it is recommended to use a series 70 ? termination resistor on every probe connector (tdi, tck, tms, tdo, pra, prb). the 70 ? series termination is used to prevent data transmission corruption during probing and reading back the checksum. table 1-8 device configuration options for probe capability (trst pin reserved) jtag mode trst 1 security fuse programmed pra, prb 2 tdi, tck, tdo 2 dedicated low no user i/o 3 probing unavailable flexible low no user i/o 3 user i/o 3 dedicated high no probe circuit outputs probe circuit inputs flexible high no probe circuit outputs probe circuit inputs ? ? yes probe circuit secured probe circuit secured notes: 1. if trst pin is not reserved, the device be haves according to trst=high in the table. 2. avoid using the tdi, tck, tdo, pra, and prb pins as input or bidirectional ports. since these pins are active during probing, input signals will not pass through thes e pins and may cause contention. 3. if no user signal is assigned to these pins, they will behave as unused i/os in th is mode. unused pins are automatically tris tated by actel?s designer software. figure 1-13 silicon explorer ii probe setup serial connection additional 16 channels (logic analyzer) silicon explorer ii tdi tck tms 16 pin connection 22 pin connection pra prb tdo ex fpgas
ex family fpgas 1-12 v4.2 development tool support the ex family of fpgas is fu lly supported by both actel's libero? integrated design environment and designer fpga development software. actel libero ide is a design management environment th at streamlines the design flow. libero ide provides an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. additionally, libero ide allows users to integrate both schematic and hdl synthesis into a single flow and verify the entire design in a single environment. libero ide includes synplify? for acte l from synplicity?, viewdraw for actel from mentor graphics, modelsim? hdl simulator from mentor graphics?, waveformer lite? from synapticad?, and designer software from actel. refer to the libero ide flow (located on actel?s website) diagram for more information. actel's designer software is a place-and-route tool and provides a comprehensive suit e of backend support tools for fpga development. the designer software includes timing-driven place-and-r oute, and a world-class integrated static timing an alyzer and constraints editor. with the designer software, a user can lock his/her design pins before layout while minimally impacting the results of place-and-route. additionally, the back- annotation flow is compat ible with all the major simulators and the simulation results can be cross-probed with silicon explorer ii, actel?s integrated verification and logic analysis tool. anot her tool included in the designer software is the actgen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or hdl design. actel's designer software is compatible with the most popular fpga design entry and verification tools from companies such as me ntor graphics, synplicity, synopsys, and cadence design systems. the designer software is available for both the windows and unix operating systems. related documents datasheet ex automotive family fpgas http://www.actel.com/d ocuments/exautods.pdf application notes maximizing logic utilization in ex, sx and sx-a fpga devices using cc macros http://www.actel.com/doc uments/maxlogicutil.pdf actel's implementation of secu rity in actel antifuse fpgas http://www.actel.com/documents/ antifusesecurityan.pdf actel ex, sx-a, and rt54sx-s i/os http://www.actel.com/docum ents/antifuseioan.pdf actel sx-a and rt54sx-s devi ces in hot-swap and cold- sparing applications http://www.actel.com/documents/ hotswapcoldsparing.pdf design for low power in actel antifuse fpgas http://www.actel.com/d ocuments/lowpower.pdf programming actel devices http://www.actel.com/documents/ programmingguide.pdf user guides silicon sculptor ii user's guide http://www.actel.com /techdocs/manuals/ default.asp#programmers miscellaneous libero ide flow http://www.actel.com/products/tools/libero/flow.html
ex family fpgas v4.2 1-13 2.5v/3.3v/5.0v operating conditions table 1-9 absolute maximum ratings* symbol parameter limits units v cci dc supply voltage for i/os ?0.3 to +6.0 v v cca dc supply voltage for array ?0.3 to +3.0 v v i input voltage ?0.5 to +5.75 v v o output voltage ?0.5 to +v cci v t stg storage temperature ?65 to +150 c note: *stresses beyond those listed u nder ?absolute maximum ratings? may cause pe rmanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliab ility. devices should not be operated outside th e recommended operating conditions. table 1-10 recommended operating conditions parameter commercial industrial units temperature range* 0 to +70 ?40 to +85 c 2.5v power supply range (v cca , v cci ) 2.3-2.7 2.3-2.7 v 3.3v power supply range (v cci ) 3.0-3.6 3.0-3.6 v 5.0v power supply range (v cci ) 4.75-5.25 4.75-5.25 v note: *ambient te mperature (t a ). table 1-11 typical ex standby current at 25c product v cca = 2.5v v cci = 2.5v v cca = 2.5v v cci = 3.3v v cca = 2.5v v cci = 5.0v ex64 397 a497 a700 a ex128 696 a795 a 1,000 a ex256 698 a796 a 2,000 a
ex family fpgas 1-14 v4.2 2.5v lvcmos2 electrical specifications symbol commercial industrial parameter min. max. min. max. units v oh v cci = min, v i = v ih or v il (i oh = -100 a) 2.1 2.1 v v cci = min, v i = v ih or v il (i oh = -1 ma) 2.0 2.0 v v cci = min, v i = v ih or v il (i oh = -2 ma) 1.7 1.7 v v ol v cci = min, v i = v ih or v il (i ol = 100 a) 0.2 0.2 v v cci = min, v i = v ih or v il (i ol = 1ma) 0.4 0.4 v v cci = min,v i = v ih or v il (i ol = 2 ma) 0.7 0.7 v v il input low voltage, v out v ol(max) ?0.3 0.7 -0.3 0.7 v v ih input high voltage, v out v oh(min) 1.7 v cci + 0.3 1.7 v cci + 0.3 v i il / i ih input leakage current, v in = v cci or gnd ?10 10 ?10 10 a i oz 3-state output leakage current, v out = v cci or gnd ?10 10 ?10 10 a t r , t f 1,2 input transition time 10 10 ns c io i/o capacitance 10 10 pf i cc 3,4 standby current 1.0 3.0 ma iv curve can be derived from the ibis mode l at www.actel.com/cust sup/models/ibis.html. notes: 1. t r is the transition time from 0.7 v to 1.7v. 2. t f is the transition time from 1.7v to 0.7v. 3. i cc max commercial ?f = 5.0ma 4. i cc = i cci + i cca
ex family fpgas v4.2 1-15 3.3v lvttl electrical specifications 5.0v ttl electrical specifications symbol parameter commercial industrial min. max. min. max. units v oh v cci = min, v i = v ih or v il (i oh = ?8ma) 2.4 2.4 v v ol v cci = min, v i = v ih or v il (i ol = 12ma) 0.4 0.4 v v il input low voltage 0.8 0.8 v v ih input high voltage 2.0 v cci +0.5 2.0 v cci +0.5 v i il / i ih input leakage current, v in = v cci or gnd ?10 10 ?10 10 a i oz 3-state output leakage current, v out = v cci or gnd ?10 10 ?10 10 a t r , t f 1,2 input transition time 10 10 ns c io i/o capacitance 10 10 pf i cc 3,4 standby current 1.5 10 ma iv curve can be derived from the ibis mode l at www.actel.com/custsup/models/ibis.html. notes: 1. t r is the transition time from 0.8 v to 2.0v. 2. t f is the transition time from 2.0v to 0.8v. 3. i cc max commercial ?f=5.0ma 4. i cc = i cci + i cca symbol parameter commercial industrial min. max. min. max. unit s v oh v cci = min, v i = v ih or v il (i oh = ?8ma) 2.4 2.4 v v ol v cci = min, v i = v ih or v il (i ol = 12ma) 0.4 0.4 v v il input low voltage 0.8 0.8 v v ih input high voltage 2.0 v cci +0.5 2.0 v cci +0.5 v i il / i ih input leakage current, v in = v cci or gnd ?10 10 ?10 10 a i oz 3-state output leakage current, v out = v cci or gnd ?1010?1010a t r , t f 1,2 input transition time 10 10 ns c io i/o capacitance 10 10 pf i cc 3,4 standby current 15 20 ma iv curve can be derived from the ibis mode l at www.actel.com/custsup/models/ibis.html note: 1. t r is the transition time from 0.8 v to 2.0v. 2. t f is the transition time from 2.0v to 0.8v. 3. i cc max commercial ?f=20ma 4. i cc = i cci + i cca
ex family fpgas 1-16 v4.2 power dissipation power consumption for ex devices can be divided into two components: static and dynamic. static power component the power due to standby cu rrent is typically a small component of the overall power. typical standby current for ex devices is listed in the table 1-11 on page 1-13 . for example, the typical static power for ex128 at 3.3v v cci is: i cc * v cca = 795a x 2.5v = 1.99mw dynamic power component power dissipation in cmos devices is usually dominated by the dynamic power dissipation. this component is frequency-dependent and a function of the logic and the external i/o. dynamic power dissipation results from charging internal chip capacitance due to pc board traces and load device inputs. an additional component of the dynamic power diss ipation is the totem pole current in the cmos transistor pairs. the net effect can be associated with an equiva lent capacitance that can be combined with frequency and voltage to represent dynamic power dissipation. dynamic power dissipation = ceq * v cca 2 x f where: equivalent capacitance is calculated by measuring i cca at a specified frequency and voltage for each circuit component of interest. meas urements have been made over a range of frequencies at a fixed value of v cc . equivalent capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. equivalent capacitance values are shown below. ceq values for ex devices the variable and fixed capacitance of other device components must also be taken into account when estimating the dynamic power dissipation. table 1-12 shows the capacitance of the clock components of ex devices. the estimation of the dynamic power dissipation is a piece-wise linear summation of the power dissipation of each component. dynamic power dissipation = v cca 2 * [(m c * c eqcm * fm c ) comb modules + (m s * c eqsm * fm s ) seq modules + (n * c eqi * fn) input buffers + (0.5 * (q1 * c eqcr * fq1) + (r1 * fq1)) rclka + (0.5 * (q2 * c eqcr * fq2) + (r2 * fq2)) rclkb + (0.5 * (s1 * c eqhv * fs1)+(c eqhf * fs1)) hclk ] + v cci 2 * [(p * (c eqo + c l ) * fp) output buffers ] where: ceq = equivalent capacitance f = switching frequency combinatorial modules (ceqcm) 1.70pf sequential modules (ceqsm) 1.70pf input buffers (ceqi) 1.30pf output buffers (ceqo) 7.40pf routed array clocks (ceqcr) 1.05pf table 1-12 capacitance of clock components of ex devices ex64 ex128 ex256 dedicated array clock ? variable (ceqhv) 0.85pf 0.85pf 0.85pf dedicated array clock ? fixed (ceqhf) 18.00pf 20.00pf 25.00pf routed array clock a (r1) 23.00pf 28.00pf 35.00pf routed array clock b (r2) 23.00pf 28.00pf 35.00pf m c = number of combinatorial cells switching at frequency fm, typically 20% of c-cells m s = number of sequential cells switching at frequency fm, typically 20% of r-cells n = number of input buffers switching at frequency fn, typically number of inputs / 4 p = number of output buffers switching at frequency fp, typically number of outputs / 4 q1 = number of r-cells driven by routed array clock a q2 = number of r-cells driven by routed array clock b r1 = fixed capacitance due to routed array clock a r2 = fixed capacitance due to routed array clock b s1 = number of r-cells driven by dedicated array clock c eqcm = equivalent capacitance of combinatorial modules
ex family fpgas v4.2 1-17 the ex, sx-a and rtsx-s powe r calculator can be used to estimate the total power dissipation (static and dynamic) of ex devices and can be found at http://www.actel.com/products/rescenter/power/ calculators.asp . thermal characteristics the temperature variable in the designer software refers to the junction temper ature, not the ambient temperature. this is an impo rtant distinction because the heat generated from dynamic power consumption is usually hotter than th e ambient temperature. eq 1-1 , shown below, can be used to calculate junction temperature. eq 1-1 junction temperature = ? t + t a (1) where: t a = ambient temperature ? t = temperature gradient between junction (silicon) and ambient = ja * p p = power ja = junction to ambient of package. ja numbers are located in the "package thermal characteristics" section below. package thermal characteristics the device junction-to-case thermal characteristic is jc , and the junction-to-ambien t air characteristic is ja . the thermal characteristics for ja are shown with two different air flow rates. jc is provided for reference. the maximum junction temperature is 150 c. the maximum power dissipation allowed for ex devices is a function of ja . a sample calculatio n of the absolute maximum power dissipation allowed for a tqfp 100-pin package at commercial temp erature and still air is as follows: c eqsm = equivalent capacitance of sequential modules c eqi = equivalent capacitance of input buffers c eqcr = equivalent capacitance of routed array clocks c eqhv = variable capacitance of dedicated array clock c eqhf = fixed capacitance of dedicated array clock c eqo = equivalent capacitance of output buffers c l = average output loading capacitance, typically 10pf fm c = average c-cell switching frequency, typically f/10 fm s = average r-cell switching frequency, typically f/10 fn = average input buff er switching frequency, typically f/5 fp = average output buff er switching frequency, typically f/5 fq1 = frequency of routed clock a fq2 = frequency of routed clock b fs1 = frequency of dedicated array clock package type pin count jc ja units still air 1.0 m/s 200 ft/min 2.5 m/s 500 ft/min thin quad flat pack (tqfp) 64 12.0 42.4 36.3 34.0 c/w thin quad flat pack (tqfp) 100 14.0 33.5 27.4 25.0 c/w chip scale package (csp) 49 72.2 59.5 54.1 c/w chip scale package (csp) 128 54.1 44.6 40.6 c/w chip scale package (csp) 180 57.8 47.6 43.3 c/w maximum power allowed max. junction temp. ( c) max. ambient temp. ( c) ? ja ( c/w) ------------------------------------------------------------------------------------------------------------------------------- -- 150 c70 c ? 33.5 c/w ---------------------------------- - 2.39w = = =
ex family fpgas 1-18 v4.2 ex timing model hardwired clock external setup = t inyh + t ird1 + t sud ? t hckh = 0.7 + 0.3 + 0.5 ? 1.1 = 0.4 ns clock-to-out (pad-to-pad), typical =t hckh + t rco + t rd1 + t dhl = 1.1 + 0.6 + 0.3 + 2.6 = 4.6 ns routed clock external setup = t inyh + t ird2 + t sud ? t rckh = 0.7 + 0.4 + 0.5 ? 1.3= 0.3 ns clock-to-out (pad-to-pad), typical =t rckh + t rco + t rd1 + t dhl = 1.3+ 0.6 + 0.3 + 2.6 = 4.8 ns note: values shown for ex128?p, worst-case comm ercial conditions (5.0v, 35pf pad load). figure 1-14 ex timing model input delays internal delays predicted routing delays output delays i/o module t inyh = 0.7 ns t ird2 = 0.4 ns t ird1 = 0.3 ns combinatorial cell i/o module t dhl = 2.6 ns t rd8 = 1.2 ns t rd4 = 0.7 ns t rd1 = 0.3 ns t pd = 0.7 ns i/o module t dhl = 2.6 ns t rd1 = 0.3 ns t rco = 0.6 ns i/o module t inyh = 1.3 ns t enzl = 1.9 ns t sud = 0.5 ns t hd = 0.0 ns t sud = 0.5 ns t hd = 0.0 ns t rckh = 1.3 ns (100% load) t ird1 = 0.3 ns dq register cell routed clock t rd1 = 0.3 ns t rco = 0.6 ns t hckh = 1.1 ns dq register cell hard-wired clock i/o module t dhl = 2.6 ns t enzl = 1.9 ns
ex family fpgas v4.2 1-19 output buffer delays ac test loads table 1-13 output buffer delays d to ac test loads (shown below) pa d e tr ibu ff in gnd 50% out 1.5v 50% 1.5v en gnd 50% out 1.5v 50% 10% en gnd 50% out gnd 1.5v 50% 90% v ol v cc v oh t dlh t dhl v ol v cc v cc t enzl t enlz v cc v oh t enzh t enhz figure 1-15 ac test loads r to v cc for t pzl r to gnd for t phz r = 1 kw r to v cc for t plz r to gnd for t ph z r = 1 kw gnd 35 pf gnd 35 pf 5 pf to the output under test to the output under test to the output under test load 1 (used to measure propagation delay) load 2 (used to measure enable delays) load 3 (used to measure disable delays) v cc v cc
ex family fpgas 1-20 v4.2 input buffer delays c-cell delays cell timing characteristics table 1-14 input buffer delays pad y inbuf in 3v 0v 1.5v out gnd 50% 1.5v 50% t iny t iny v cc table 1-15 c-cell delays s a b y s, a or b out gnd 50% out gnd gnd 50% 50% 50% 50% 50% t pd t pd t pd t pd v cc v cc v cc figure 1-16 flip-flops (positive edge triggered) d clk clr q d clk q clr t hpwh , t wasyn t hd t hpwl , t clr t rpwl t rpwh preset t preset preset t hp t sud t rco
ex family fpgas v4.2 1-21 timing characteristics timing characteristics for ex devices fall into three categories: family-dependent, device-dependent, and design-dependent. the input and output buffer characteristics are common to all ex family members. internal routing delays are device-dependent. design dependency means actual delays are not determined until after placemen t and routing of the user?s design are complete. delay values may th en be determined by using the timer utility or performi ng simulation with post- layout delays. critical nets and typical nets propagation delays are expres sed only for typical nets, which are used for initial design performance evaluation. critical net delays can then be applied to the most timing critical paths. critical ne ts are determined by net property assignment prior to placement and routing. up to six percent of the nets in a design may be designated as critical. long tracks some nets in the design use long tracks. long tracks are special routing resources th at span multiple rows, columns, or modules. long tracks employ three to five antifuse connections. this increases capacitance and resistance, resulting in lo nger net delays for macros connected to long tracks. typically, no more than six percent of nets in a fully utilized device require long tracks. long tracks contribute approximately 4 ns to 8.4 ns delay. this additional de lay is represented statistically in higher fanout routing delays. timing derating ex devices are manufactured with a cmos process. therefore, device perfor mance varies according to temperature, voltage, and process changes. minimum timing parameters reflect maximum operating voltage, minimum operating temper ature, and best-case processing. maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and wo rst-case processing. temperature and voltage derating factors table 1-16 temperature and voltage derating factors (normalized to worst-case commercial, t j = 70 c, v cca = 2.3v) v cca junction temperature (t j ) ?55 ?40 0 25 70 85 125 2.3 0.79 0.80 0.87 0.88 1.00 1.04 1.13 2.5 0.74 0.74 0.81 0.83 0.93 0.97 1.06 2.7 0.69 0.70 0.76 0.78 0.88 0.91 1.00
ex family fpgas 1-22 v4.2 ex family timing characteristics table 1-17 ex family timing characteristics (worst-case commercial conditions, v cca = 2.3v , t j = 70 c) ??p? speed ?std? speed ??f? speed units parameter description min. max. min. max. min. max. c-cell propagation delays 1 t pd internal array module 0.7 1.0 1.4 ns predicted routing delays 2 t dc fo=1 routing delay, directconnect 0.1 0.1 0.2 ns t fc fo=1 routing delay, fastconnect 0.3 0.5 0.7 ns t rd1 fo=1 routing delay 0.3 0.5 0.7 ns t rd2 fo=2 routing delay 0.4 0.6 0.8 ns t rd3 fo=3 routing delay 0.5 0.8 1.1 ns t rd4 fo=4 routing delay 0.7 1.0 1.3 ns t rd8 fo=8 routing delay 1.2 1.7 2.4 ns t rd12 fo=12 routing delay 1.7 2.5 3.5 ns r-cell timing t rco sequential clock-to-q 0.6 0.9 1.3 ns t clr asynchronous clear-to-q 0.6 0.8 1.2 ns t preset asynchronous preset-to-q 0.7 0.9 1.3 ns t sud flip-flop data input set-up 0.5 0.7 1.0 ns t hd flip-flop data input hold 0.0 0.0 0.0 ns t wasyn asynchronous pulse width 1.3 1.9 2.6 ns t recasyn asynchronous recovery time 0.3 0.5 0.7 ns t hasyn asynchronous hold time 0.3 0.5 0.7 ns 2.5v input module propagation delays t inyh input data pad-to-y high 0.6 0.9 1.3 ns t inyl input data pad-to-y low 0.8 1.1 1.5 ns 3.3v input module propagation delays t inyh input data pad-to-y high 0.7 1.0 1.4 ns t inyl input data pad-to-y low 0.9 1.3 1.8 ns 5.0v input module propagation delays t inyh input data pad-to-y high 0.7 1.0 1.4 ns t inyl input data pad-to-y low 0.9 1.3 1.8 ns input module predicted routing delays 2 t ird1 fo=1 routing delay 0.3 0.4 0.5 ns t ird2 fo=2 routing delay 0.4 0.6 0.8 ns t ird3 fo=3 routing delay 0.5 0.8 1.1 ns t ird4 fo=4 routing delay 0.7 1.0 1.3 ns t ird8 fo=8 routing delay 1.2 1.7 2.4 ns t ird12 fo=12 routing delay 1.7 2.5 3.5 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t rco + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance.
ex family fpgas v4.2 1-23 table 1-18 ex family timing characteristics (worst-case commercial conditions v cca = 2.3v, v cci = 4.75v, t j = 70c) ??p? speed ?std? speed ??f? speed parameter description min. max. min. max. min. max. units dedicated (hard-wired) array clock networks t hckh input low to high (pad to r-cell input) 1.1 1.6 2.3 ns t hckl input high to low (pad to r-cell input) 1.1 1.6 2.3 ns t hpwh minimum pulse width high 1.4 2.0 2.8 ns t hpwl minimum pulse width low 1.4 2.0 2.8 ns t hcksw maximum skew <0.1 <0.1 <0.1 ns t hp minimum period 2.8 4.0 5.6 ns f hmax maximum frequency 357 250 178 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) max. 1.1 1.6 2.2 ns t rckl input high to low (light load) (pad to r-cell input) max. 1.0 1.4 2.0 ns t rckh input low to high (50% load) (pad to r-cell input) max. 1.2 1.7 2.4 ns t rckl input high to low (50% load) (pad to r-cell input) max. 1.2 1.7 2.4 ns t rckh input low to high (100% load) (pad to r-cell input) max. 1.3 1.9 2.6 ns t rckl input high to low (100% load) (pad to r-cell input) max. 1.3 1.9 2.6 ns t rpwh min. pulse width high 1.5 2.1 3.0 ns t rpwl min. pulse width low 1.5 2.1 3.0 ns t rcksw 1 maximum skew (light load) 0.2 0.3 0.4 ns t rcksw 1 maximum skew (50% load) 0.1 0.2 0.3 ns t rcksw 1 maximum skew (100% load) 0.1 0.1 0.2 ns note: 1. clock skew improves as the clock network becomes more heavily loaded.
ex family fpgas 1-24 v4.2 table 1-19 ex family timing characteristics (worst-case commercial conditions v cca = 2.3v, v cci = 2.3v or 3.0v, t j = 70c) ??p? speed ?std? speed ??f? speed parameter description min. max. min. max. min. max. units dedicated (hard-wired) array clock networks t hckh input low to high (pad to r-cell input) 1.1 1.6 2.3 ns t hckl input high to low (pad to r-cell input) 1.1 1.6 2.3 ns t hpwh minimum pulse width high 1.4 2.0 2.8 ns t hpwl minimum pulse width low 1.4 2.0 2.8 ns t hcksw maximum skew <0.1 <0.1 <0.1 ns t hp minimum period 2.8 4.0 5.6 ns f hmax maximum frequency 357 250 178 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) max. 1.0 1.4 2.0 ns t rckl input high to low (light load) (pad to r-cell input) max. 1.0 1.4 2.0 ns t rckh input low to high (50% load) (pad to r-cell input) max. 1.2 1.7 2.4 ns t rckl input high to low (50% load) (pad to r-cell input) max. 1.2 1.7 2.4 ns t rckh input low to high (100% load) (pad to r-cell input) max. 1.4 2.0 2.8 ns t rckl input high to low (100% load) (pad to r-cell input) max. 1.4 2.0 2.8 ns t rpwh min. pulse width high 1.4 2.0 2.8 ns t rpwl min. pulse width low 1.4 2.0 2.8 ns t rcksw 1 maximum skew (light load) 0.2 0.3 0.4 ns t rcksw 1 maximum skew (50% load) 0.2 0.2 0.3 ns t rcksw 1 maximum skew (100% load) 0.1 0.1 0.2 ns note: 1. clock skew improves as the clock network becomes more heavily loaded.
ex family fpgas v4.2 1-25 table 1-20 ex family timing characteristics (worst-case commercial conditions v cca = 2.3v, t j = 70c) ??p? speed ?std? speed ??f? speed parameter description min. ma x. min. max. min. max. units 2.5v lvcmos output module timing 1 (v cci = 2.3v) t dlh data-to-pad low to high 3.3 4.7 6.6 ns t dhl data-to-pad high to low 3.5 5.0 7.0 ns t dhls data-to-pad high to low?low slew 11.6 16.6 23.2 ns t enzl enable-to-pad, z to l 2.5 3.6 5.1 ns t enzls enable-to-pad z to l?low slew 11.8 16.9 23.7 ns t enzh enable-to-pad, z to h 3.4 4.9 6.9 ns t enlz enable-to-pad, l to z 2.1 3.0 4.2 ns t enhz enable-to-pad, h to z 2.4 5.67 7.94 ns d tlh delta delay vs. load low to high 0.034 0.046 0.066 ns/pf d thl delta delay vs. load high to low 0.016 0.022 0.05 ns/pf d thls delta delay vs. load high to low?low slew 0.05 0.072 0.1 ns/pf 3.3v lvttl output module timing 1 (v cci = 3.0v) t dlh data-to-pad low to high 2.8 4.0 5.6 ns t dhl data-to-pad high to low 2.7 3.9 5.4 ns t dhls data-to-pad high to low?low slew 9.7 13.9 19.5 ns t enzl enable-to-pad, z to l 2.2 3.2 4.4 ns t enzls enable-to-pad z to l?low slew 9.7 13.9 19.6 ns t enzh enable-to-pad, z to h 2.8 4.0 5.6 ns t enlz enable-to-pad, l to z 2.8 4.0 5.6 ns t enhz enable-to-pad, h to z 2.6 3.8 5.3 ns d tlh delta delay vs. load low to high 0.02 0.03 0.046 ns/pf d thl delta delay vs. load high to low 0.016 0.022 0.05 ns/pf d thls delta delay vs. load high to low?low slew 0.05 0.072 0.1 ns/pf 5.0v ttl output module timing 1 (v cci = 4.75v) t dlh data-to-pad low to high 2.0 2.9 4.0 ns t dhl data-to-pad high to low 2.6 3.7 5.2 ns t dhls data-to-pad high to low?low slew 6.8 9.7 13.6 ns t enzl enable-to-pad, z to l 1.9 2.7 3.8 ns t enzls enable-to-pad z to l?low slew 6.8 9.8 13.7 ns t enzh enable-to-pad, z to h 2.1 3.0 4.1 ns t enlz enable-to-pad, l to z 3.3 4.8 6.6 ns note: 1. delays based on 35 pf loading.
ex family fpgas 1-26 v4.2 pin description clka/b routed clock a and b these pins are clock inpu ts for clock distribution networks. input levels are co mpatible with standard ttl or lvttl specifications. the cl ock input is buffered prior to clocking the r-cells. if not used, this pin must be set low or high on the board. it must not be left floating. gnd ground low supply voltage. hclk dedicated (hardwired) array clock this pin is the clock input for sequential modules. input levels are compatible with standard ttl or lvttl specifications. this input is directly wired to each r-cell and offers clock speeds independent of the number of r- cells being driven. if not used, this pin must be set low or high on the board. it must not be left floating. i/o input/output the i/o pin functions as an input, output, tristate, or bidirectional buffer. based on certain configurations, input and output levels are compatible with standard ttl or lvttl specificatio ns. unused i/o pins are automatically tristated by the designer software. lp low power pin controls the low power mode of the ex devices. the device is placed in the low power mode by connecting the lp pin to logic high. in low power mode, all i/os are tristated, all input buffers are turned off, and the core of the device is turned off. to exit the low power mode, the lp pin must be set low. the device enters the low power mode 800 ns after the lp pin is driven to a logic high. it will resume normal operation 200 s after the lp pin is driven to a logic low. nc no connection this pin is not connected to circuitry within the device. these pins can be driven to any voltage or can be left floating with no effect on the operation of the device. pra/prb, i/o probe a/b the probe pin is used to ou tput data from any user- defined design node within the device. this diagnostic pin can be used independently or in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device. the probe pin can be used as a user-defined i/o when verification has been completed. the pin?s probe capabilities can be permanently disabled to protect programmed design confidentiality. tck, i/o test clock test clock input for diagnostic probe and device programming. in flexible mode, tck becomes active when the tms pin is set low (refer to table 1-4 on page 1-9 ). this pin functions as an i/o when the boundary scan state machine reaches the ?logic reset? state. tdi, i/o test data input serial input for boundary scan testing and diagnostic probe. in flexible mode, tdi is active when the tms pin is set low (refer to table 1-4 on page 1-9 ). this pin functions as an i/o when the boundary scan state machine reaches the ?logic reset? state. tdo, i/o test data output serial output for boundary scan testing. in flexible mode, tdo is active when the tms pin is set low (refer to table 1-4 on page 1-9 ). this pin functions as an i/o when the boundary scan state ma chine reaches the "logic reset" state. when silicon explorer is being used, tdo will act as an output when the "checksum" command is run. it will return to user i/o when "checksum" is complete. tms test mode select the tms pin controls th e use of the ieee 1149.1 boundary scan pins (tck, td i, tdo, trst). in flexible mode when the tms pin is set low, the tck, tdi, and tdo pins are boundary sc an pins (refer to table 1-4 on page 1-9 ). once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the ?logic reset? state. at this point, the boundary scan pins will be released and will function as regular i/o pins. the ?logic reset? state is reached five tck cycles after the tms pin is set high. in dedicated test mode, tms functions as specified in the ieee 1149.1 specifications. trst, i/o boundary scan reset pin once it is configured as the jtag reset pin, the trst pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. the trst pin is equipped with an internal pull-up resistor. this pin functions as an i/o when the ?reserve jtag reset pin? is not selected in the designer software. v cci supply voltage supply voltage for i/os. v cca supply voltage supply voltage for array.
ex family fpgas v4.2 2-1 package pin assignments 64-pin tqfp figure 2-1 64-pin tqfp 1 64-pin tqfp 64
ex family fpgas 2-2 v4.2 64-pin tqfp pin number ex64 function ex128 function 1gndgnd 2 tdi, i/o tdi, i/o 3i/oi/o 4 tms tms 5gndgnd 6v cci v cci 7i/oi/o 8i/oi/o 9nci/o 10 nc i/o 11 trst, i/o trst, i/o 12 i/o i/o 13 nc i/o 14 gnd gnd 15 i/o i/o 16 i/o i/o 17 i/o i/o 18 i/o i/o 19 v cci v cci 20 i/o i/o 21 prb, i/o prb, i/o 22 v cca v cca 23 gnd gnd 24 i/o i/o 25 hclk hclk 26 i/o i/o 27 i/o i/o 28 i/o i/o 29 i/o i/o 30 i/o i/o 31 i/o i/o 32 tdo, i/o tdo, i/o note: *please read the lp pin desc riptions for restrictions on their use 33 gnd gnd 34 i/o i/o 35 i/o i/o 36 v cca v cca 37 v cci v cci 38 i/o i/o 39 i/o i/o 40 nc i/o 41 nc i/o 42 i/o i/o 43 i/o i/o 44 v cca v cca 45* gnd/lp gnd/ lp 46 gnd gnd 47 i/o i/o 48 i/o i/o 49 i/o i/o 50 i/o i/o 51 i/o i/o 52 v cci v cci 53 i/o i/o 54 i/o i/o 55 clka clka 56 clkb clkb 57 v cca v cca 58 gnd gnd 59 pra, i/o pra, i/o 60 i/o i/o 61 v cci v cci 62 i/o i/o 63 i/o i/o 64 tck, i/o tck, i/o 64-pin tqfp pin number ex64 function ex128 function note: *please read the lp pin desc riptions for restrictions on their use
ex family fpgas v4.2 2-3 100-pin tqfp figure 2-2 100-pin tqfp (top view) 1 100 100-pin tqfp
ex family fpgas 2-4 v4.2 100-pin tqfp pin number ex64 function ex128 function ex256 function 1 gnd gnd gnd 2 tdi, i/o tdi, i/o tdi, i/o 3ncnci/o 4ncnci/o 5ncnci/o 6 i/o i/o i/o 7tmstmstms 8v cci v cci v cci 9 gnd gnd gnd 10 nc i/o i/o 11 nc i/o i/o 12 i/o i/o i/o 13 nc i/o i/o 14 i/o i/o i/o 15 nc i/o i/o 16 trst, i/o trst, i/o trst, i/o 17 nc i/o i/o 18 i/o i/o i/o 19 nc i/o i/o 20 v cci v cci v cci 21 i/o i/o i/o 22 nc i/o i/o 23 nc nc i/o 24 nc nc i/o 25 i/o i/o i/o 26 i/o i/o i/o 27 i/o i/o i/o 28 i/o i/o i/o 29 i/o i/o i/o 30 i/o i/o i/o 31 i/o i/o i/o 32 i/o i/o i/o 33 i/o i/o i/o 34 prb, i/o prb, i/o prb, i/o note: *please read the lp pin desc riptions for restrictions on their use 35 v cca v cca v cca 36 gnd gnd gnd 37 nc nc nc 38 i/o i/o i/o 39 hclk hclk hclk 40 i/o i/o i/o 41 i/o i/o i/o 42 i/o i/o i/o 43 i/o i/o i/o 44 v cci v cci v cci 45 i/o i/o i/o 46 i/o i/o i/o 47 i/o i/o i/o 48 i/o i/o i/o 49 tdo, i/o tdo, i/o tdo, i/o 50 nc i/o i/o 51 gnd gnd gnd 52 nc nc i/o 53 nc nc i/o 54 nc nc i/o 55 i/o i/o i/o 56 i/o i/o i/o 57 v cca v cca v cca 58 v cci v cci v cci 59 nc i/o i/o 60 i/o i/o i/o 61 nc i/o i/o 62 i/o i/o i/o 63 nc i/o i/o 64 i/o i/o i/o 65 nc i/o i/o 66 i/o i/o i/o 67 v cca v cca v cca 68 gnd/lp gnd/lp gnd/lp 100-pin tqfp pin number ex64 function ex128 function ex256 function note: *please read the lp pin desc riptions for restrictions on their use
ex family fpgas v4.2 2-5 69 gnd gnd gnd 70 i/o i/o i/o 71 i/o i/o i/o 72 nc i/o i/o 73 nc nc i/o 74 nc nc i/o 75 nc nc i/o 76 nc i/o i/o 77 i/o i/o i/o 78 i/o i/o i/o 79 i/o i/o i/o 80 i/o i/o i/o 81 i/o i/o i/o 82 v cci v cci v cci 83 i/o i/o i/o 84 i/o i/o i/o 85 i/o i/o i/o 86 i/o i/o i/o 87 clka clka clka 88 clkb clkb clkb 89 nc nc nc 90 v cca v cca v cca 91 gnd gnd gnd 92 pra, i/o pra, i/o pra, i/o 93 i/o i/o i/o 94 i/o i/o i/o 95 i/o i/o i/o 96 i/o i/o i/o 97 i/o i/o i/o 98 i/o i/o i/o 99 i/o i/o i/o 100 tck, i/o tck, i/o tck, i/o 100-pin tqfp pin number ex64 function ex128 function ex256 function note: *please read the lp pin desc riptions for restrictions on their use
ex family fpgas 2-6 v4.2 49-pin csp figure 2-3 49-pin csp (top view) 1 2 3 4 5 6 7 a b c d e f g a1 ball pad corner
ex family fpgas v4.2 2-7 49-pin csp pin number ex64 function ex128 function a1 i/o i/o a2 i/o i/o a3 i/o i/o a4 i/o i/o a5 v cca v cca a6 i/o i/o a7 i/o i/o b1 tck, i/o tck, i/o b2 i/o i/o b3 i/o i/o b4 pra, i/o pra, i/o b5 clka clka b6 i/o i/o b7* gnd/lp* gnd/lp* c1 i/o i/o c2 tdi, i/o tdi, i/o c3 v cci v cci c4 gnd gnd c5 clkb clkb c6 v cca v cca c7 i/o i/o d1 i/o i/o d2 tms tms d3 gnd gnd d4 gnd gnd note: *please read the lp pin desc riptions for restrictions on their use. d5 v cca v cca d6 i/o i/o d7 i/o i/o e1 i/o i/o e2 trst, i/o trst, i/o e3 v cci v cci e4 gnd gnd e5 i/o i/o e6 i/o i/o e7 v cci v cci f1 i/o i/o f2 i/o i/o f3 i/o i/o f4 i/o i/o f5 hclk hclk f6 i/o i/o f7 tdo, i/o tdo, i/o g1 i/o i/o g2 i/o i/o g3 i/o i/o g4 prb, i/o prb, i/o g5 v cca v cca g6 i/o i/o g7 i/o i/o 49-pin csp pin number ex64 function ex128 function note: *please read the lp pin desc riptions for restrictions on their use.
ex family fpgas 2-8 v4.2 128-pin csp figure 2-4 128-pin csp (top view) 1 2 34 56 7 8 9 10 11 12 a b c d e f g h j k l m a1 ball pad corner
ex family fpgas v4.2 2-9 128-pin csp pin number ex64 function ex128 function ex256 function a1 i/o i/o i/o a2 tck, i/o tck, i/o tck, i/o a3 v cci v cci v cci a4 i/o i/o i/o a5 i/o i/o i/o a6 v cca v cca v cca a7 i/o i/o i/o a8 i/o i/o i/o a9 v cci v cci v cci a10 i/o i/o i/o a11 i/o i/o i/o a12 i/o i/o i/o b1 tms tms tms b2 i/o i/o i/o b3 i/o i/o i/o b4 i/o i/o i/o b5 i/o i/o i/o b6 pra, i/o pra, i/o pra, i/o b7 clkb clkb clkb b8 i/o i/o i/o b9 i/o i/o i/o b10 i/o i/o i/o b11 gnd gnd gnd b12 i/o i/o i/o c1 i/o i/o i/o c2 tdi, i/o tdi, i/o tdi, i/o c3 i/o i/o i/o c4 i/o i/o i/o c5 i/o i/o i/o c6 clka clka clka c7 i/o i/o i/o c8 i/o i/o i/o c9 i/o i/o i/o note: *please read the lp pin desc riptions for restrictions on their use. c10 nc i/o i/o c11 nc i/o i/o c12 i/o i/o i/o d1 nc i/o i/o d2 i/o i/o i/o d3 i/o i/o i/o d4 i/o i/o i/o d5 i/o i/o i/o d6 gnd gnd gnd d7 i/o i/o i/o d8 gnd gnd gnd d9 i/o i/o i/o d10 i/o i/o i/o d11 i/o i/o i/o d12 v cci v cci v cci e1 nc i/o i/o e2 v cci v cci v cci e3 i/o i/o i/o e4 gnd gnd gnd e9 gnd gnd gnd e10 i/o i/o i/o e11* gnd/lp* gnd/lp* gnd/lp* e12 v cca v cca v cca f1 nc i/o i/o f2 nc i/o i/o f3 nc i/o i/o f4 i/o i/o i/o f9 gnd gnd gnd f10 nc i/o i/o f11 i/o i/o i/o f12 i/o i/o i/o g1 nc i/o i/o g2 trst, i/o trst, i/o trst, i/o 128-pin csp pin number ex64 function ex128 function ex256 function note: *please read the lp pin desc riptions for restrictions on their use.
ex family fpgas 2-10 v4.2 g3 i/o i/o i/o g4 gnd gnd gnd g9 gnd gnd gnd g10 nc i/o i/o g11 i/o i/o i/o g12 nc i/o i/o h1 gnd gnd gnd h2 i/o i/o i/o h3 v cci v cci v cci h4 gnd gnd gnd h9 i/o i/o i/o h10 v cci v cci v cci h11 v cca v cca v cca h12 nc i/o i/o j1 nc nc v cca j2 i/o i/o i/o j3 v cci v cci v cci j4 i/o i/o i/o j5 i/o i/o i/o j6 i/o i/o i/o j7 gnd gnd gnd j8 i/o i/o i/o j9 gnd gnd gnd j10 i/o i/o i/o j11 i/o i/o i/o j12 nc i/o i/o k1 nc i/o i/o k2 i/o i/o i/o k3 i/o i/o i/o k4 i/o i/o i/o k5 i/o i/o i/o k6 prb, i/o prb, i/o prb, i/o k7 hclk hclk hclk 128-pin csp pin number ex64 function ex128 function ex256 function note: *please read the lp pin desc riptions for restrictions on their use. k8 i/o i/o i/o k9 i/o i/o i/o k10 i/o i/o i/o k11 tdo, i/o tdo, i/o tdo, i/o k12 i/o i/o i/o l1 i/o i/o i/o l2 i/o i/o i/o l3 nc i/o i/o l4 i/o i/o i/o l5 i/o i/o i/o l6 i/o i/o i/o l7 i/o i/o i/o l8 i/o i/o i/o l9 i/o i/o i/o l10 i/o i/o i/o l11 nc i/o i/o l12 v cci v cci v cci m1 gnd gnd gnd m2 i/o i/o i/o m3 i/o i/o i/o m4 i/o i/o i/o m5 i/o i/o i/o m6 i/o i/o i/o m7 v cca v cca v cca m8 i/o i/o i/o m9 i/o i/o i/o m10 i/o i/o i/o m11 i/o i/o i/o m12 i/o i/o i/o 128-pin csp pin number ex64 function ex128 function ex256 function note: *please read the lp pin desc riptions for restrictions on their use.
ex family fpgas v4.2 2-11 180-pin csp figure 2-5 180-pin csp 1 2 345 67 8 9 10 11 12 13 14 a b c d e f g h j k l m n p a1 ball pad corner
ex family fpgas 2-12 v4.2 180-pin csp pin number ex256 function a1 i/o a2 i/o a3 gnd a4 nc a5 nc a6 nc a7 nc a8 nc a9 nc a10 nc a11 nc a12 i/o a13 i/o a14 i/o b1 i/o b2 i/o b3 tck, i/o b4 v cci b5 i/o b6 i/o b7 v cca b8 i/o b9 i/o b10 v cci b11 i/o b12 i/o b13 i/o b14 i/o c1 i/o c2 tms c3 i/o c4 i/o note: *please read the lp pin descriptions for restrictions on their use. c5 i/o c6 i/o c7 pra, i/o c8 clkb c9 i/o c10 i/o c11 i/o c12 gnd c13 i/o c14 i/o d1 i/o d2 i/o d3 tdi, i/o d4 i/o d5 i/o d6 i/o d7 clka d8 i/o d9 i/o d10 i/o d11 i/o d12 i/o d13 i/o d14 i/o e1 i/o e2 i/o e3 i/o e4 i/o e5 i/o e6 i/o e7 gnd e8 i/o 180-pin csp pin number ex256 function note: *please read the lp pin descriptions for restrictions on their use. e9 gnd e10 i/o e11 i/o e12 i/o e13 v cci e14 i/o f1 i/o f2 i/o f3 v cci f4 i/o f5 gnd f10 gnd f11 i/o f12* gnd/lp* f13 v cca f14 i/o g1 v cca g2 i/o g3 i/o g4 i/o g5 i/o g10 gnd g11 i/o g12 i/o g13 i/o g14 v cca h1 i/o h2 i/o h3 trst, i/o h4 i/o h5 gnd h10 gnd 180-pin csp pin number ex256 function note: *please read the lp pin descriptions for restrictions on their use. h11 i/o h12 i/o h13 i/o h14 i/o j1 i/o j2 gnd j3 i/o j4 v cci j5 gnd j10 i/o j11 v cci j12 v cca j13 i/o j14 i/o k1 i/o k2 v cca k3 i/o k4 v cci k5 i/o k6 i/o k7 i/o k8 gnd k9 i/o k10 gnd k11 i/o k12 i/o k13 i/o k14 i/o l1 i/o l2 i/o l3 i/o l4 i/o 180-pin csp pin number ex256 function note: *please read the lp pin descriptions for restrictions on their use.
ex family fpgas v4.2 2-13 l5 i/o l6 i/o l7 prb, i/o l8 hclk l9 i/o l10 i/o l11 i/o l12 tdo, i/o l13 i/o l14 i/o m1 i/o m2 i/o m3 i/o m4 i/o m5 i/o m6 i/o m7 i/o m8 i/o m9 i/o m10 i/o m11 i/o m12 i/o m13 v cci m14 i/o n1 i/o n2 gnd n3 i/o n4 i/o n5 i/o n6 i/o n7 i/o n8 v cca 180-pin csp pin number ex256 function note: *please read the lp pin descriptions for restrictions on their use. n9 i/o n10 i/o n11 i/o n12 i/o n13 i/o n14 i/o p1 i/o p2 i/o p3 i/o p4 nc p5 nc p6 nc p7 nc p8 nc p9 nc p10 nc p11 nc p12 gnd p13 i/o 180-pin csp pin number ex256 function note: *please read the lp pin descriptions for restrictions on their use.

ex family fpgas v4.2 3-1 datasheet information list of changes the following table lists critical changes that were made in the current version of the document. previous version changes in current version (v4.2) page v4.1 the "ex timing model" was updated. 1-18 v4.0 the "development tool support" section was updated. 1-12 the "package thermal characteristics" section was updated. 1-17 v3.0 the "product profile" section was updated. 1-i the "ordering information" section was updated. 1-ii the "temperature grade offerings" section is new. 1-ii the "speed grade and temperature grade matrix" section is new. 1-ii the "general description" section was updated. 1-1 the "clock resources" section was updated. 1-4 table 1-1 connections of routed clock networks, clka and clkb is new. 1-4 the "user security" section was updated. 1-5 the "i/o modules" section was updated. 1-5 the "hot swapping" section was updated. 1-6 the "power requirements" section was updated. 1-6 the "low power mode" section was updated. 1-6 the "boundary scan testing (bst)" section was updated. 1-9 the "dedicated test mode" section was updated. 1-9 the "flexible mode" section was updated. 1-9 table 1-5 boundary-scan pin configurations and functions is new. 1-9 the "trst pin" section was updated. 1-9 the "probing capabilities" section is new. 1-10 the "programming" section was updated. 1-10 the "probing capabilities" section was updated. 1-10 the "silicon explorer ii probe" section was updated. 1-10 the "design considerations" section was updated. 1-11 the "development tool support" section was updated. 1-12 the "absolute maximum ratings*" section was updated. 1-13 the "temperature and voltage derating factors" section was updated. 1-21 the "tdi, i/o test data input" section was updated. 1-26 the "tdo, i/o test data output" section was updated. 1-26 the "tms test mode select" section was updated. 1-26 the "trst, i/o boundary scan reset pin" section was updated. 1-26
ex family fpgas 3-2 v4.2 v3.0 all vsv pins were changed to v cca . the change affected the following pins: 64-pin tqfp ?pin 36 100-pin tqfp ?pin 57 49-pin csp ?pin d5 128-pin csp?pin h11 and pin j1 for ex256 180-pin csp ?pins j12 and k2 v2.0.1 the "recommended operating conditions" section has been changed. 1-13 the "3.3v lvttl electrical specifications" section has been updated. 1-15 the "5.0v ttl electrical sp ecifications" section has been updated. 1-15 the "total dynamic power (mw)" section is new. 1-8 the "system power at 5%, 10%, and 15% duty cycle" section is new. 1-8 the "ex timing model" section has been updated. 1-18 advanced v0.4 the i/ o features table, table 1-2 on page 1-5 , was updated. 1-5 the table, "standby power of ex devices in lp mode typical conditions, vcca, vcci = 2.5v, tj = 25 c" section , was updated. 1-6 "typical ex standby current at 25c" section is a new table. 1-13 the table in the section, "package thermal charac teristics" section has been updated for the 49-pin csp. 1-17 the "ex timing model" section has been updated. 1-18 the timing numbers found in, "ex family timing characteristics" section have been updated. 1-22 the v sv pin has been added to the "pin description" section . 1-26 please see the following pin tables for the v sv pin and an important footnote including the pin: "64-pin tqfp" , "100-pin tqfp" ,, , "128-pin csp" , and "180-pin csp" . 2-1 , 2-3 , 2-6 , 2-11 the figure, "64-pin tqfp" section has been updated. 2-1 advanced v0.3 in the product profile , the maximum user i/os for ex64 was changed to 84. 1-i in the product profile table, the maximum user i/os for ex128 was changed to 100. 1-i advanced v0.2 the mechanical draw ings section has been removed fr om the data sheet. the mechanical drawings are now contained in a separate document, ?package characteristics and mechanical drawings ,? available on the actel web site. a new section describing "clock resources" has been added. 1-4 a new table describing "i/o features" has been added. 1-5 the "pin description" section has been updated and clarified. 1-26 the original electrical specific ations table was separated in to two tables (2.5v and 3.3/ 5.0v). in both tables, several diff erent currents are specified for v oh and v ol . page 8 and 9 a new table listing 2.5v low power specifications and associated power graphs were added. page 9 pin functions for ex256 tq100 have been added to the "100-pin tqfp" table. 2-3 a cs49 pin drawing and pin assignment table including ex64 and ex128 pin functions have been added. page 26 a cs128 pin drawing and pin assignment table including ex64, ex128, and ex256 pin functions have been added. pages 26-27 a cs180 pin drawing and pin assignment table for ex256 pin functions have been added. pages 27, 31 advanced v.1 the following table note was added to the ex timing characteristic s table for clarification: clock skew improves as the clock ne twork becomes more heavily loaded. pages 14-15
ex family fpgas v4.2 3-3 datasheet categories in order to provide the latest information to designers, some datasheets are published before data has been fully characterized. datasheets are desi gnated as "product brief," "advance d," "production," and "datasheet supplement." the definitions of these categories are as follows: product brief the product brief is a summarized version of a datasheet (advanced or production) containing general product information. this brief gives an overview of specific device and family information. advanced this datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. unmarked (production) this datasheet version contains informat ion that is considered to be final. datasheet supplement the datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. the supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications th at do not differ between the two families.
5172154-7/06.04 http://www.actel.com actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners. actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa phone 650.318.4200 fax 650.318.4600 actel europe ltd. dunlop house, riverside way camberley, surrey gu15 3yl united kingdom phone +44 (0)1276 401 450 fax +44 (0) 1276 401 490 actel japan exos ebisu bldg. 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan phone +81.03.3445.7671 fax +81.03.3445.7668 actel hong kong 39th floor, on e pacific place 88 queensway, admiralty hong kong phone +852.227.35712 fax +852.227.35999

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